The invention relates to a Coded Mark Inversion CMI, decoder for converting CMI-coded signals into binary signals by means of a delay element and a subsequently added gating network.
The CMI code is known from the CCITT recommendation G703 in which it is provided for the 140-Mbit/sec interfaces in the hierarchical structure of digital signal transmission. This code is a two-state NRZ code for which a zero signal is represented by the combination of a negative pulse of half-bit width, while the one signals appear alternatively as +1 signals of full-bit width.
A typical CMI decoder is disclosed in the Hewlett-Packard Company Service Manual for the test device "Error Detector" HP 3763 A, shown in FIG. A4-3, part 2. This known CMI decoder has two differential amplifiers arranged on the input side, with the output of one of the differential amplifiers connected directly to a gating network consisting of five OR-NOR gates, and the output of the other differential amplifier connected to that gating network via switchable delay elements. This results in a comparatively elaborate design in which high power consumption may become a problem for configurations using a remote power supply.
For monitoring CMI-coded signals, it has been suggested that the level of the input signal or a timing signal derived from it should be monitored. Since the receive level depends on the length and the status of the interface circuit as well as the content of the binary signal, no clearly defined monitoring results are provided. For example, even an interruption of the outer conductor of a coaxial cable will usually not result in a lowering of the level suitable for monitoring due to the use of controlled input equalizers with corresponding system reserve.
Nevertheless, such an interruption will result in incorrect equalization at the receive end due to the high degree of shifting in the equalizer's operating point; also, a drastic decrease in the signal-to-noise ratio will result without causing an error message.